MMCT BYPASS SHELL

NAME	SIZE	PREMISSION
0000:00:15.0:pcie001	DIR	drwxr-xr-x
0000:00:15.1:pcie001	DIR	drwxr-xr-x
0000:00:15.2:pcie001	DIR	drwxr-xr-x
0000:00:15.3:pcie001	DIR	drwxr-xr-x
0000:00:15.4:pcie001	DIR	drwxr-xr-x
0000:00:15.5:pcie001	DIR	drwxr-xr-x
0000:00:15.6:pcie001	DIR	drwxr-xr-x
0000:00:15.7:pcie001	DIR	drwxr-xr-x
0000:00:16.0:pcie001	DIR	drwxr-xr-x
0000:00:16.1:pcie001	DIR	drwxr-xr-x
0000:00:16.2:pcie001	DIR	drwxr-xr-x
0000:00:16.3:pcie001	DIR	drwxr-xr-x
0000:00:16.4:pcie001	DIR	drwxr-xr-x
0000:00:16.5:pcie001	DIR	drwxr-xr-x
0000:00:16.6:pcie001	DIR	drwxr-xr-x
0000:00:16.7:pcie001	DIR	drwxr-xr-x
0000:00:17.0:pcie001	DIR	drwxr-xr-x
0000:00:17.1:pcie001	DIR	drwxr-xr-x
0000:00:17.2:pcie001	DIR	drwxr-xr-x
0000:00:17.3:pcie001	DIR	drwxr-xr-x
0000:00:17.4:pcie001	DIR	drwxr-xr-x
0000:00:17.5:pcie001	DIR	drwxr-xr-x
0000:00:17.6:pcie001	DIR	drwxr-xr-x
0000:00:17.7:pcie001	DIR	drwxr-xr-x
0000:00:18.0:pcie001	DIR	drwxr-xr-x
0000:00:18.1:pcie001	DIR	drwxr-xr-x
0000:00:18.2:pcie001	DIR	drwxr-xr-x
0000:00:18.3:pcie001	DIR	drwxr-xr-x
0000:00:18.4:pcie001	DIR	drwxr-xr-x
0000:00:18.5:pcie001	DIR	drwxr-xr-x
0000:00:18.6:pcie001	DIR	drwxr-xr-x
0000:00:18.7:pcie001	DIR	drwxr-xr-x

bind	4 KB	--w-------
uevent	4 KB	--w-------
unbind	4 KB	--w-------


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